1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. In particular, the present invention relates to a capacitor in a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
In typical semiconductor manufacturing processes, a capacitor within a semiconductor device is manufactured using polysilicon as an electrode material. In general, a Metal-Insulator-Metal (MIM) capacitor comprises a first polysilicon layer, a second polysilicon layer, and a number of metal wiring layers. However, MIM capacitors with a large capacitance require metal wiring layers having a large area.
FIGS. 1A through 1J are sectional views illustrating a conventional method of fabricating a MIM capacitor of a semiconductor device. As shown in FIG. 1A, a first interlayer insulation film 13 is formed on a semiconductor substrate 11. A first Ti/TiN layer 15 is formed on the first interlayer insulation film 13 at a thickness of 200 to 600 Å. The Ti portion of the first Ti/TiN layer 15 is used as an adhesive layer, and the TiN portion is used as a diffusion preventing film. A first Al layer 17 is formed on the first Ti/TiN layer 15 at a thickness of 4000 to 5000 Å. A second Ti/TiN film 19 is then formed on the first Al layer 17 at a thickness of 300 to 700 Å. The Ti layer of the second Ti/TiN layer 19 is used as an adhesive layer, and the TiN layer is used as an anti-reflection film. A dielectric film 21 is formed on the second Ti/TiN layer 19 at a thickness of 500 to 1500 Å. The dielectric film 21 is made of SiOxNy, Si3N4 or an oxide formed by a plasma enhanced chemical vapor deposition (“PECVD”) method. An upper-electrode thin film 23 is formed on the dielectric film 21 at a thickness of 1000 to 3000 Å. The upper-electrode thin film 23 is formed using an Al layer, a Ti/TiN layer or a stacked structure of Al and Ti/TiN layers.
Referring now to FIG. 1B, a first photosensitive film pattern 25 is formed on the upper-electrode thin film 23 to expose a predetermined portion for an upper electrode. Referring now to FIG. 1C, an upper electrode 24 and a dielectric film pattern 22 is formed by etching the upper-electrode thin film 23 and the dielectric film 21 using the first photosensitive film pattern 25 as an etching mask. The upper-electrode thin film 23 is etched in a dry-etching process using plasma activated by a mixture gas of Cl2/BCl3 as a primary etching gas and N2 gas as an additive gas. The dielectric film 21 is etched using a dry-etching process using plasma activated by a CxFy gas as a primary etching gas and CHF3, O2 or Ar as an additive gas. The first photosensitive film pattern 25 is then removed.
Referring now to FIG. 1D, a second photosensitive film pattern 27 which protects a predetermined portion for a lower metal wiring is formed on the entire surface. A lower metal wiring having a stacked structure of the second Ti/TiN layer pattern 20, the first Al layer pattern 18 and the first Ti/TiN layer pattern 16 is formed by etching the second Ti/TiN layer 19, the first Al layer 17 and the first Ti/TiN layer 15 using the second photosensitive film pattern 27 as an etching mask. The etching is carried out using a dry-etching process using plasma activated by a mixture gas of Cl2/BCl3 as a primary etching gas and N2 gas as an additive gas.
Referring now to FIG. 1E, the second photosensitive film pattern 27 is then removed. Referring now to FIG. 1F, a second interlayer insulation film 29 is formed on the entire surface. The second interlayer insulation film 29 is formed of SiO2, SiO2-δ, Spin-On-Glass (SOG) or Flowable Oxide (FOx). A Chemical Mechanical Polishing (CMP) is used to planarize and adjust the thickness of the second interlayer insulation film 29.
Referring now to FIG. 1G, a third photosensitive film pattern 31 is formed on the second interlayer insulation film 29 to expose predetermined portions for via-contacts. Referring now to FIG. 1H, via-contact holes 33a-33c are formed by etching the second interlayer insulation film 29 using the third photosensitive film pattern 31 as an etching mask. The etching is carried out using a dry-etching process using plasma activated by a CxFy gas. If the etching is excessive, the entire upper layer 24 may be etched. The third photosensitive film pattern 31 is then removed.
Referring now to FIG. 1I, a via-contact plug 35 is formed by depositing a tungsten layer on the entire surface and performing a CMP process or an etch-back process using plasma. The via-contact plug 35 is connected to the upper electrode 24.
Referring now to FIG. 1J, an upper metal wiring having a stacked structure comprising a fourth Ti/TiN layer pattern 41, a second Al layer pattern 39 and a third Ti/TiN layer pattern 37 is formed by sequentially forming and then etching a third Ti/TiN layer (not shown), a second Al layer (not shown) and a fourth Ti/TiN layer (not shown) on the entire surface using an upper metal wiring mask as an etching mask. Accordingly, a MIM capacitor 43 is formed as indicated by the area surrounded by the dotted line.
Unfortunately, the conventional method of fabricating the MIM capacitor and the semiconductor device has several disadvantages. The stepped structure due to the dielectric film pattern and the upper electrode makes it difficult to use a fine pattern when forming the photosensitive film pattern for the lower metal pattern. A separate mask process and etching process is required to form the upper electrode, which also complicates the manufacturing process. In addition, a considerable amount of the upper electrode is lost due to the depth difference between the via-contact holes formed on the upper electrode and the via-contact holes formed on the lower metal electrode, which deteriorates the operational characteristics and process yield of the device.
It is, therefore, desired to provide a semiconductor device and a method of fabricating the same that address the above and other shortcomings of the prior art.